Many of today's shrinking consumer electronic devices, such as cellular telephones, digital video cameras, global positioning systems, personal audio/video players, and personal data assistants, require many functions to be packaged in a very small area of a printed wiring board. In attempting to use the area on the printed wiring boards more efficiently, semiconductor chip manufacturers have recently been switching from larger, more cumbersome interconnection conventions, such as pin grid arrays (“PGAs”) and the perimeter leaded quad flat packs (“QFPs”), to smaller conventions, such as ball grid arrays (“BGAs”). Using BGA technology, semiconductor chips are typically interconnected to their supporting substrates using solder connections, such as with “flip-chip” technology. However, when solder alone is used to interconnect the chip contacts to the substrate, the columns of solder are generally designed to be short to maintain the solder's structural integrity. This results in minimal elastic solder connection properties, which further results in increased susceptibility to solder cracking due to the mechanical stress of the differential coefficient of thermal expansion (“CTE”) of the chip relative to the supporting substrate, thereby reducing the reliability of the solder joint.
In other words, when the chip heats up during use, both the chip and the substrate expand; and when the heat is removed, both the chip and the substrate contract. The problem that arises is that the chip and the substrate expand and contract at different rates and at different times, thereby stressing the interconnections between them. As the features of semiconductor chips continue to be reduced in size, the number of chips packed into a given area will be greater and the heat dissipated by the each of these chips will have a greater effect on the thermal mismatch problem. This further increases the need for a highly compliant interconnection scheme for the chips.
The solder cracking problem is exacerbated when more than one semiconductor chip is mounted in a package, such as in a multichip module. Multichip modules continue to grow in popularity; however, as more chips are packaged together, more heat will be dissipated by each package which, in turn, means the interconnections between a package and its supporting substrate will encounter greater mechanical stress due to thermal cycling. Further, as more chips are integrated into multichip modules, each package requires additional interconnections thereby increasing overall rigidity of the connection between the module and its supporting substrate.
Another issue for the multichip modules is manufacturability. As the number of integrated circuits in the package increases, it becomes more difficult to achieve good manufacturing yields. A single failed component included in the stack will make the entire stack bad. With the increasing number of functions included in the most popular consumer electronic devices, it becomes imperative that the manufacturing yield be optimized.
Thus, a need still remains for an integrated circuit package stacking system. In view of the constant demand for more functions in less space on the printed wiring boards, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.